1. Field of the Invention
This invention relates to a method of manufacturing improved master-slice LSIs which require a reliable fine-wiring process.
2. Description of the Related Art
Master-slice integrated circuits (master-slice LSIs) are suitable for manufacturing IC devices of a small number and various kinds, such as analog and digital ICs. This "master-slice" means a wafer in which many kinds of ICs are preformed, i.e., a plurality of transistor elements and the like are preformed. In a master slice, nodes (which correspond to e.g. a source, a drain, and a gate of a MOS transistor) of each transistor are independent from each other, i.e., not connected to each other. Desired circuit wiring including wiring between such nodes is performed in a later process for forming metal layers. This wiring process is called "customizing process", in which circuits having various functions required by the user are formed.
In recent years, the following problems have occurred in accordance with development of LSI fine processing and with increase in the application of the technique:
First, a decrease in the reliability of IC devices has occurred in accordance with the development of refining technique of metal wiring layers In particular, electro or stress migration has become remarkable in a metal layer made of an aluminum alloy, which may cause a breakage in the layer. To avoid the breakage, it is considered to enlarge or thicken the minimum dimension of the metal layer. This, however, is unfavorable since it prevents refinement of LSIs.
Second, it is difficult to form high density devices such as a ROM (Read Only Memory), a RAM (Random Access Memory) etc.
In master-slice LSIs each having a gate array and a SRAM (Static RAM), or a gate array and a DRAM (Dynamic RAM), a base block for a logic gate and a base block for a memory are provided separately. Since a memory and a desired logical circuit are formed at the time of customization, large wiring regions are necessary, and also lots of time is required for designing the master slice.
Further, in general, considering the structure of a memory, the memory is formed inevitably in a limited manner if it is provided in the vicinity of a sense amplifier, etc. Also, the pattern of the wiring of the memory base block is simple, and it does not require such a high degree of freedom as the wiring pattern of the gate array base block. Thus, it is considered advantageous in the reliability of wiring and the designing efficiency thereof that wiring is performed for the memory portion in the stage of forming the master slice.
As is described above, in the conventional master slice, it is difficult to realize elements required in accordance with the development of the LSI refining process and with an increase in practical application, i.e., elements of high density which can have metal wiring layers of high reliability formed in a later wiring process.